It is well known that chaotic systems have rich dynamic behaviors, which are sensitive to perturbation or instability. In recent years, there has been a new research direction in chaos application that is exploiting the rich patterns inherent in the chaotic systems to do chaos computing. Chaos computing has attracted great interest since it provides a new reconfigurable logic operation scheme, where different logic operations are easily converted by the slight change of the parameters in a chaotic system. This provides a possible way to implement dynamic logic operation architecture. In the process of logic operation, the system structure itself changes dynamically. Therefore, chaotic logic devices have many advantages over the traditional logic ones, in the areas such as more security, more flexible and lower power cost.^[1–6] Recently, the most fundamental computing functions based on chaotic elements have been implemented in many experimental and theoretical researches. For example, in 2003, Murali et al. put forward the implementation scheme of NOR gate based on logistic map.^[1] In 2006, they constructed the dynamic logic gates and realized all logic operations in a single discrete-time chaotic system.^[2] In 2008, using the logistic map, Yang et al. proposed dynamic logic gates by designing three thresholds and using the different analog-logic mapping relations between the output signals.^[3] In 2010, Peng et al. provided a chaotic logic operation scheme in a drive-response chaotic synchronization system in a nonlinear circuit.^[4] In 2015, Beyki and Yaghoobi explored a new chaotic logic gate implementation scheme by using genetic algorithm.^[5]

The chaotic logic operations in a semiconductor laser system have many advantages over those in the nonlinear circuit system, in some aspects such as wider bandwidth, faster response speed, higher security, and lower power cost. Optical chaotic logic operations are the most critical technology in future optical chaotic network secure communication, however, the technology of the optical chaotic logic operations still lags behind. And it has received little attention and is still in the initial stage of research. For most of the logic processing of optical chaotic signals, such as multiplexing, demultiplexing, switching, regeneration, storage and calculation, it is necessary to implement all-optical chaotic logic devices and sequential logic ones with low power consumption and high speed. Vertical cavity surface emitting laser (VCSEL), as a microchip semiconductor laser, exhibits many advantages over edge emitting laser, in some areas such as low threshold current, single longitudinal mode operation, high modulation frequency, low cost and large-scale integration into two-dimensional arrays.^[7–13] There are two polarization components (PCs) in the VCSEL with the spin flip mode (SMF),^[14] due to the weak material and cavity anisotropies. Much effort has been devoted to the observation of the polarization-bistability (PB) of the VCSEL subjected to different polarization light feedbacks and injection current sweep rates.^[7–10] The PB has a faster response time than the absorption bistability. It is very attractive that the all-optical chaotic logic operations (AOCLOs) with low power and high speed can be implemented by using the PB of the optically injected VCSEL.

Several researches have been done to explore logic gates by using the chaotic synchronization between two semiconductor lasers^[11–15] or the PB of the VCSEL^[16–31] In 2013, according to a master-slave-response synchronization system of chaotic multiple-quantum-well lasers, Yan proposed the computing methods of chaotic XNOR, NOR, NOT logic gates,^[11] and implemented optoelectronic NOR and XNOR logic gates by using parallel synchronization of three chaotic lasers.^[13] Recently, different types of chaotic logic gates have been explored by using the PB of the optically injected VCSEL in different setups.^[7–10]

However, at present, most of optical chaotic logic operations are implemented under static conditions.^{[7–13,16,20,32]} Since the VCSEL with external optical feedback or external optical injection, as a nonlinear system with high dimension, has not only rich nonlinear dynamic behaviors, but also generates PB. It is great prospect that reconfigurable dynamic AOCLOs are implemented by using the rich patterns of the optically injected VCSEL and its PB. However, there are many fundamental scientific problems that need solving in this field, such as the ability to restructure AOCLOs, the constraint relations between chaotic logic operations and the key parameters of the VCSEL, the selection of logic control signal, etc. Motivated by these problems, in an optically injected VCSEL, we explore the dynamic evolutions of the PB with some key parameters such as the bias current, the light injected strength, the frequency detuning of the injected field and the VCSEL. We further propose the implementation steps for reconfigurable dynamic AOCLOs, and elaborate the ability to reconstruct basic AOCLOs, such as AND, NAND, OR, NOR, XOR, XNOR. The rest of this paper is organized as follows. In Section 2 we give the schematic diagram of AOCLOs in an optically injected VCSEL, and present the corresponding theory model. In Section 3 we present the results and discuss the implementation of basic AOCLOs, and demonstrates their reconfiguration abilities. Finally, we draw some conclusions from the present study in Section 4.

Using the rich patterns in a chaotic system based on the optically injected VCSEL, the implementation scheme for AOCLOs is put forward as shown in Fig. 1. Figure 1(a) and 1(b) show the principle block diagram and light paths in detail, respectively. In Fig. 1(a), when the optically injected VCSEL is considered as a chaotic processor, the chaotic states of the output two PCs depend on the following rate equations:^[15] 1 2 3 4 Here, , , and represent the first order differential; f represents a function; x and y represent the x-PC and the y-PC emitted by the VCSEL, respectively; E_x(t) and E_y(t) are the amplitudes of the x-PC and the y-PC, respectively; I is the injected light amplitude and is the sum of two square waves that encode two logic inputs, i.e., I = I₁ + I₂; the control parameter C equals the sum of two square waves that encode two control logic signals, i.e., C = C₁ + C₂; N is the total carrier concentration; n is the difference in concentration between spin-up carriers and spin-down carriers. Since that the chaotic-state of the output x-PC and y-PC are varied simultaneously when the chaotic processor is subjected to the injection of external light, the output x-PC and y-PC are considered as two logic outputs, defined as X and Y, respectively. Suppose that the mean square errors (MSEs) of E_x(t) and E_y(t) are defined as σ_x and σ_y, and their thresholds are fixed at and , respectively, we obtain that X = 0 and Y = 0 if and ; X = 1 and Y = 1 when and . To implement AOCLOs, we put forward the technical steps below.

Fig. 1.

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Fig. 1. (color online) Schematic diagram of all-optical chaotic logic operations in an optically injected VCSEL, showing (a) principle block diagram; (b) detailed light paths; SG-DBR laser: sampled grating distributed Bragg reflector laser; VCSEL: vertical cavity surface emitting laser; IS: isolator; μ: normalized injection current of VCSEL; μ0: normalized injection current of SG-DBR laser; EAM: electric amplifier; PD: photo-detector; BS: beam splitter; PBS: polarization beam splitter; HWP: half-wave plate; FR: faraday rotator; CP: coupler; VA: variable attenuator; LPBF: low pass Bessel filter; FPGA: field programmable gate array; parameters σx* and σy*: thresholds of x-PC and y-PC respectively; i: electric signal.

An all-optical logic operation can be realized when C meets a certain logic relation between I₁ and I₂. When the steps 2-4 above are repeated, the others can be performed by varying the logic operation of C between two inputs. According to the above-mentioned principle, Fig. 1(b) gives the detailed light path for the implementation of AOCLOs. Here, the center wavelength of the VCSEL is 1550 nm; the optical isolator 1 (IS₁) is used to avoid the light from the polarization beam splitter 1 (PBS₁) to feedback into the SG-DBR laser; the IS₂ is used to avoid the light from the PBS₂ to feedback into the VCSEL; the variable attenuator 3 (VA₃) and the VA₄ are used to control the injected strengths of the x-PC and the y-PC, respectively. The wavelength of sampled grating distributed Bragg reflector (SG-DBR) laser is tuned by the injection current. The light emitted by the SG-DBR laser is divided into two beams by the beam splitter 1 (BS₁). They are again separated into two beams of light with the same energy by the 1×2 BS₂ and 1×2 BS₃, respectively. So, the amplitudes of two beams of light from the BS₂ are represented by E_inj1, and those from the BS₃ are denoted as E_inj2. The E_inj1 and E_inj2 are used to encode two logic inputs I₁ and I₂, respectively. E_inj1 and E_inj2 are varied by the VA₁ and VA₂, respectively, but unvaried with the injection current μ₀. Here, the frequency detunings Δω₁ and Δω₂ between the SG-DBR laser and the VCSEL are used to encode two control logic signals C₁ and C₂, respectively, where Δω₁ and Δω₂ are generated by the injection currents μ₀₁ and μ₀₂, respectively. To implement AOCLOs, the control signal needs to meet different logic relations between two logic inputs. So, it will be varied with the logic inputs for different all-optical logic operations. How to synchronize the control signal with the logic inputs is a key problem. For this purpose, we propose a scheme to solve the problem as follows. One beam of light with the amplitude of E_inj1 from the BS₂ is converted into the electric signal i₁ by the photo-detector 1 (PD₁). The i₁ is amplified by electric amplifier 1(EAM₁), the noise in it from the PD₁ is filtered out by the low pass Bessel filter 1. The electric signal i₂ converted by the light with the amplitude of E_inj2 is processed in the same way. The i₁ and i₂ are encoded into two electric logic inputs, which are logically consistent with the I₁ and I₂, respectively. Moreover, the injection current μ₀ is encoded into the logic output Y₀ of the field programmable gate array (FPGA). If μ₀ = μ₀₁, Y₀ = 0, correspondingly, Δω = Δω₁ (C = C₁); when μ₀ = μ₀₂, Y₀ = 1. As a result, Δω = Δω₂(C = C₂). By using the FPGA, the μ₀ can be implemented by different logic operations between the i₁ and i₂, such as logic AND, OR, NAND, NOR, XOR, and XNOR operation. In this way, the control logic C can be realized indirectly by different logic operations between the two optical logic inputs I₁ and I₂. For each logic operation, the control logic C can also be changed synchronously with the optical logic inputs. Therefore, it is prospective that AOCLOs can be further performed by varying the logic relation of the control signal between the two logic inputs.

In addition, the polarized direction of the SG-DBR laser may emerge in an arbitrary direction. To ensure the polarized light from the SG-DBR to be accurately injected into the x-PC and the y-PC of the VCSEL, respectively, the polarized light from the SG-DBR needs converting into linear polarization light by some optical passive devices placed between the coupler 1 (CP₁) and the VCSEL. Here we consider the converted linear polarization light is the x-PC. For this purpose, the arbitrary polarized light from CP₁ is separated into the x-PC and y-PC by the PBS₁. The x-PC from the PBS₁ is directly injected into CP₂. The y-PC from the PBS₁ is firstly switched into the x-PC by the faraday rotator 1 (FR₁) and half wave plate 1 (HWP₁), then injected into the CP₂. Thus, the light from the CP₂ is ensured to be the x-PC, and is split into two beams by BS₄. One of the two beams is directly injected into the x-PC of the VCSEL, the other is firstly converted into the y-PC by FR₂ and HWP₂, then injected into the y-PC of the VCSEL. The injected x-PC and y- PC have the same amplitude. Their amplitudes are considered as logic inputs. With a fixed bias current, the output x-PC and y-PC from the VCSEL are a digital chaotic wave, and set to be two logic outputs, X and Y. Besides, in Fig. 1(b), the rate-equations. (1)–(4) are replaced by the following specific expressions:^[14] 5 6 7 8 where x and y represent the x-PC and the y-PC, respectively; E is the normalized amplitude, , with g being the differential material gain, A is the slowly varying amplitude; N is the total carrier concentration; n is the difference in concentration between carriers with spin-up and carriers with spin-down; k is the field decay rate; γ_e is the decay rate of N; γ_s is the spin-flip relaxation rate; a is the linear enhancement factor; γ_a is the linear dichroism; γ_p is the linear birefringence; μ = (Γg/k)[U/(2eVγ_e) − N₀] (μ is the normalized injection current which equals 1 at the lasing threshold current); V is the volume of the active layer, Γ is the field confinement factor to the active region, e is the electron charge, U is the injected current, N₀ is the half the transparency carrier density; D is the noise strength parameter and defined as , with β_sp being the spontaneous emission factor; ξ_x and ξ_y are two independent Gaussian white noises with the mean value of 0 and the variance of 1, and their correlation coefficients are 〈ξ_i(t)ξ_j(t)*〉 = 2δ_ijδ(t − t′). Here, the above-mentioned parameters are considered above the threshold value; K_x and K_y are the injection strengths of the x-PC and y-PC, respectively. is the normalized amplitude of the injected field, which is the sum of E_inj1 and E_inj2. A_inj is the slowly varying amplitude of the injected field; the frequency detuning of the injected field Δω = ω_inj – ω_ref, ω_inj is the optical angular frequency of the injected field, and the reference angular frequency ω_ref is defined as (ω_x + ω_y)/2, with ω_x and ω_y being the angular optical frequency of the x-polarization and the y-polarization of the free-running VCSEL, respectively. Here, ω_x = −γ_p + aγ_a, ω_y = γ_p − aγ_a.

Using the fourth-order Runge–Kutta method, we firstly calculate Eqs. (5)–(8). The numerical values in calculation are presented in Table 1. Figure 2 shows the polarization-resolved P–U curve for the free-running 1550-nm-VCSEL. It can be seen from this diagram that the threshold current U_th is 6.8 mA. When U = 6.8 mA, only the y-PC begins to oscillate; for 6.8 mA < U < 7.6 mA, the y-PC continues to oscillate; when U > 7.6 mA, the x-PC will oscillate while the y-PC begins to be suppressed; for U > 7.76 mA, the x-PC continues to oscillates and the y-PC is suppressed completely.

Fig. 2.

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	Fig. 2. (color online) P–U curve for a free running 1550-nm-VCSEL, where the red dash line represents x-polarization component (x-PC) and the blue solid line refers to y-polarization component (y-PC). Here, Ix = |Ex|2, Iy = |Ey|2.

According to Step 1, in this work, we take the frequency detuning Δω as the control parameter C, and consider the injected amplitude E_ing as logic input. With the aim of implementing AOCLOs, we calculate the mapping of the dynamic states of the x-PC and that of the y-PC in the parameter space of E_inj and Δω under K_x = 0 ns⁻¹ and K_y = 10 ns⁻¹ (see Fig. 3). From this diagram, one sees that some typical dynamical states such as period-one oscillation (P₁), period-two oscillation (P₂), quasi-periodic oscillation (QP) and chaotic state (CO) can be observed, through regulating E_inj and Δω. Here, Δω₁ = 40 GHz and Δω₂ = −20 GHz are considered as two components of C (C₁ and C₂), respectively. Correspondingly, the values of logic output Y of the FPGA are 1 and 0, respectively (see Fig. 1). So we mainly concern the chaotic region under Δω₁ = 40 GHz and Δω₂ = −20 GHz. By carefully observing Fig. 3(a), for Δω₁ = 40 GHz, while E_inj varies in several spaces such as 0.1–0.28, 0.41–0.48, and 0.59–0.74, the output x-PC is in CO. The output y-PC presents CO when E_inj varies from 0.1 to 0.36, or from 0.39 to 0.52, or from 0.57 to 2.18; If Δω₂ = −20 GHz, the output x-PC shows CO when E_inj is in turn between 0.1 and 0.36, 0.38 and 2.23, as well as 2.43 and 3. The output y-PC exhibits CO while E_inj varies from 0.1 to 2.56.

Fig. 3.

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	Fig. 3. (color online) Mappings of dynamic states in the parameter space of Δω and Einj under Kx = 0 ns−1, Ky = 10 ns−1, μ = 2.0. Here, CO: chaotic state; QP: quasi-periodic oscillation; P1: period-one oscillation; P2: period–two oscillation.

Table 1.

Table 1.

Table 1. Numerical values for all-optical chaotic logic operations. . The parameter and symbol value The parameter and symbol value Line-width enhancement factor a 3 The noise strength D 108 The field decay rate k 300 ns−1 Field confinement factor to the active region Γ 0.5 Spin relaxation rate γs 50 ns−1 One half of transparency carrier density N 8 × 1023 m−3 Nonradiative carrier relaxation rate γe 1 ns−1 Volume of the active layer V 21.206 μm3 Dichroism γa 2 ns−1 The duration of the bit T 10 ns Birefringence γp 60 ns−1 The slowly varying amplitude of the injected field Ainj 1.114 × 1010 m−3/2 The normalization pump current μ 2.0 Threshold current of VCSEL Uth 6.8 mA Injection strength of x polarization Kx 0 ns−1 The differential material gain g 2.9 × 10−12 m3·s−1 Injection strength of y polarization Ky 10 ns−1 The injection strength Einj II 0.67 Center wavelength λ 1550 nm The injection strength Einj III 0.72 The injection strength Einj I 0.62

Table 1. Numerical values for all-optical chaotic logic operations. .

To obtain the optimal value of I in Step 1, in the following, we take Δω₁ = 40 GHz for an example to calculate the dynamic evolutions of the PB with some different key parameters such as μ, K_x, and K_y. Figure 4 gives the evolutions of the PB with μ, where the scanning period of E_inj is 10 ns. One sees from Fig. 4 that for the x-PC and the y-PC, with the further increase of the injection current, their bistability-loops (BLs) shift toward the direction of E_inj increasing. When μ increases to 2, the BLs are located in the range of E_inj from 0.32 to 0.73, where the outputs x-PC and the y-PC may be in CO, or P₂, or QP (see Fig. 3).

Fig. 4.

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	Fig. 4. (color online) Variations of the polarization bistabilities with Einj for different values of μ, where Kx = 0 ns−1, Ky = 10 ns−1, T = 10 ns, and Δω1 = 40 GHz.

Figure 5 further shows the bistability evolutions of the x-PC and the y-PC with E_inj for different values of K_x, where μ = 2 and the other parameters are given in Fig. 4. From this diagram, it is found that there is no effect of K_x on the shifting of their BLs. All BLs are almost the same and located in the parameter space of E_inj from 0.37 to 0.74, where the output PCs may be in CO, or P₂, or QP (see Fig. 3). Also we calculate the evolution of the PB with K_y in Fig. 6. One sees from Fig. 6 that with K_y increasing from 3 ns⁻¹ to 20 ns⁻¹, the width of the BLs are gradually shrunk, and the BLs are shifted toward the direction of E_inj decreasing. It is noted that if K_y is fixed at 10 ns⁻¹, the BLs both occur in the range of E_inj between 0.32 and 0.74, where the output two PCs may exhibit CO, or P₂, or QP state (see Fig. 3).

Fig. 5.

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	Fig. 5. (color online) Evolutions of the polarization bistabilities with Einj for different values of Kx, where μ = 2 and the other parameters are the same as those given in Fig. 4.

Fig. 6.

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	Fig. 6. (color online) Evolutions of the polarization bistabilities with Einj for different values of Ky, where μ = 2 and the other parameters are the same as those given in Fig. 4.

Under Δω₂ = −20 GHz, the evolutions of the PB with the above-mentioned parameters have similar behaviors to those under Δω₁ = 40 GHz. To further determine the specific value of E_inj that encodes logic input, we present the bistability of the x-PC and the y-PC under Δω₁ = 40 GHz and that under Δω₂ = −20 GHz as shown in Fig. 7. From this diagram, it is found that the BLs of the x-PC and the y-PC are located at E_inj that possesses a variation range of about 0.37–0.73 to realize chaotic output when Δω₁ = 40 GHz. But for Δω₂ = −20 GHz, the BLs occur at E_inj that varies from 1.89 to 2.98, where the two outputs PCs may be in CO, or QP, or P₂, or P₁.

Fig. 7.

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	Fig. 7. (color online) Bistability of the x-PC and the y-PC under Δω1 = 40 GHz (a) and (b) that under Δω2 = −20 GHz, where the other parameters are the same as those presented in Fig. 4; the red-solid line: the x-PC; the blue-dash line: the y-PC. Arrows indicate the three-level signals used to encode the logic inputs (see text for details).

Suppose that E_inj equals the sum of two square waves that encode two logic inputs, i.e., E_inj = E_inj1 + E_inj2. Here, E_inj1 and E_inj2 are considered as logic input I₁ and I₂, respectively. Since the logic inputs can be either 0 or 1, there exist four distinct input sets: (0, 0), (0, 1), (1, 0), (1, 1). We can encode four logic input sets with three-level signals E_{inj I}, E_{inj II}, and E_{inj III}, where E_{inj II} represent the (0, 1) and (1, 0), the E_{inj I}(E_{inj II} – ΔE_inj represents the set (0, 0) and E_{inj III}(E_{inj II} + ΔE_inj) denotes the set (1, 1). The three-level signal used to vary E_inj is constant during a time interval T, and defined as bit duration time. Here, T is set to be 10 ns, i.e., the rate of all-optical logic gates is 0.1 GHz. Since that the two PCs both present chaotic states in the range of E_inj from 0.59 to 0.73 under Δω₁ = 40 GHz and Δ₂ = −20 GHz (see Fig. 3) we take E_{inj I} = 0.62, E_{inj II} = 0.67 and E_{inj III} = 0.72 as the three-level signals (see Fig. 7). Here, I₁ = 0 and I₂ = 0 when E_inj1 = 0.31 and E_inj2 = 0.31, and I₁ = 1 and I₂ = 1 if E_inj1 = 0.36 and E_inj2 = 0.36.

Furthermore, according to Step 4, the logic outputs X and Y depend on the amplitude threshold values of the outputs x-PC and the y-PC, respectively. How to determine their threshold values is the key to judging logic outputs. For this purpose, suppose that C = 0 when Δω = −20 GHz; C = 1 if Δω = 40 GHz, we consider that C has different logic operations between I₁ and I₂, such as logic AND, NAND, OR, NOR, XOR, and XNOR. For different cases of logic operation C, we calculate the maximum MSEs of the outputs x-PC and y-PC under C = 0, and their minimum MSEs under C = 1, respectively, which are displayed in Table 2. Here, the maximum MSEs of the output x-PC and y-PC are defined as σ_{x max} and σ_{y max} respectively; the corresponding minimum MSEs are defined as σ_{x min} and σ_{y min}, respectively. Considering that the logic outputs X and Y have the same threshold, i.e., , for each logic operation, we find out that the threshold M needs to satisfy the following condition (See Table 2): (σ_{x max}, σ_{y max})_max < M < (σ_{x min}, σ_{y min})_min. One sees from Table 2 that (σ_{x min}, σ_{y min})_min = 0.1182 and (σ_{x max}, σ_{y max})_max = 0.0617. Hence we take M as 0.09. It is concluded that X = 0 and Y = 0 if σ_{x min} and σ_{y min} are no more than M; X = 1 and Y = 1 when σ_{x max} and σ_{y max} are more than M.

By performing Steps 2–4, we give the implementation of the logic AND and NAND operations, as shown in Fig. 8, where the amplitude of the external injection light varies with fast three-level signals. For μ = 2.0, K_x = 0 ns⁻¹, K_y = 10 ns⁻¹, and T = 10 ns. Tables 3 and 4 show the combinations of input and output for logic AND and NAND operations, respectively. As seen from Fig. 8(a) and Table 2, if C = I₁ · I₂, σ_{x max} = 0.0285 and σ_{y max} = 0.0343 when (I₁, I₂) = (0, 0), (I₁, I₂) = (0, 1), and (I₁, I₂) = (1, 0). It is obtained that X = 0 and Y = 0, owing to the fact that σ_{x max} < M and σ_{y max} < M; if (I₁, I₂) = (1, 1), σ_{x min} = 0.1566 and σ_{y min} = 0.1696. We obtain X = 1 and Y = 1 since σ_{x min} > M and σ_{y min} > M. As a result, X = I₁· I₂ and Y = I₁ · I₂. This means that logic AND operation can be implemented successfully when C = I₁ · I₂. From Fig. 8(b) and Table 4, it is seen that the two logic outputs are both logic NAND operations when C has NAND operation between the two logic outputs, i.e. , and when .

Table 2.

Table 2.

Table 2. For different cases of logic operations C between I1 and I2, the maximum MSEs (σx max and σy max) of the outputs x-PC and y-PC under C = 0, respectively, and their minimum MSEs, σx min and σy min, under C = 1. . Different control (I1I2) = (0, 0) (I1I2) = (0, 1)/(1.0) (I1I2) = (1, 1) logic operations C σx σy C σx σy C σx σy C = I1 · I2 0 σx max = 0.0011 σy max = 0.0063 0 σx max = 0.0285 σy max = 0.0343 1 σx min = 0.1566 σy min = 0.1696 1 σx min = 0.1269 σy min = 0.1227 1 σx min = 0.1310 σy min = 0.1408 0 σx max = 0.0371 σy max = 0.0346 C = I1 +I2 0 σx max = 0.0410 σy max = 0.0591 1 σx min = 0.1314 σy min = 0.1406 1 σx min = 0.1598 σy min = 0.1690 1 σx min = 0.1182 σy min = 0.1287 0 σx max = 0.0212 σy max = 0.0336 0 σx max = 0.0015 σy max = 0.0074 C = I1 ⊕ I2 0 σx max = 0.0409 σy max = 0.0617 1 σx min = 0.1311 σy min = 0.1424 0 σx max = 0.0415 σy max = 0.0566 C = I1 ⊙ I2 1 σx min = 0.1182 σy min = 0.1287 0 σx max = 0.0285 σy max = 0.0342 1 σx min = 0.1566 σy min = 0.1696

Table 2. For different cases of logic operations C between I1 and I2, the maximum MSEs (σx max and σy max) of the outputs x-PC and y-PC under C = 0, respectively, and their minimum MSEs, σx min and σy min, under C = 1. .

Fig. 8.

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	Fig. 8. (color online) Logic AND and NAND operations, for μ = 2.0, Kx = 0 ns−1, Ky = 10 ns−1, and T = 10 ns; the black solid-line: frequency detuning Δω (control logic signal); the blue line: the y-PC; bottle green line: the x-PC; the red solid line: three-level signals.

Table 3.

Table 3.

Table 3. Combinations of input and output for logic AND operation. The logic inputs are encoded with the amplitude of the optically injected field; the logic output X is decoded with the difference between the MSEs of the x-PC and its threshold; the output Y is decoded with the difference between that of the y-PC and its threshold. . Einj(I1,I2) Control logic signal C Threshold judgment AND gate: logic output X AND gate: logic output Y Einj I(0,0) 0 σx max < M; σy max < M 0 0 Einj II(0,1) 0 σx max < M; σy max < M 0 0 Einj II(1,0) 0 σx max < M; σy max < M 0 0 Einj III(1,1) 1 σx min > M; σy min > M 1 1

Table 3. Combinations of input and output for logic AND operation. The logic inputs are encoded with the amplitude of the optically injected field; the logic output X is decoded with the difference between the MSEs of the x-PC and its threshold; the output Y is decoded with the difference between that of the y-PC and its threshold. .

Table 4.

Table 4.

Table 4. Combinations of input and output for logic NAND operation. . Einj(I1,I2) Control logic signal C Threshold judgment NAND gate: logic output X NAND gate: logic output Y Einj I(0, 0) 1 σx min > M; σx min > M 1 1 Einj II(0, 1) 1 σx min > M; σy min > M 1 1 Einj II(1, 0) 1 σx min > M; σy min > M 1 1 Einj III(1, 1) 0 σx max < M; σy max < M 0 0

Table 4. Combinations of input and output for logic NAND operation. .

Logic OR, NOR, XOR, and XNOR operations are further presented in Fig. 9, and the corresponding input-output combinations, in turn, are displayed in Tables 5–8. Here, μ = 2.0, K_x = 0 ns⁻¹, K_y = 10 ns⁻¹, and T = 10 ns. Like the implementation method of logic AND and NAND operations, the other different basic logic operations can be implemented when C meets different logic operations between two logic inputs. For example, X = I₁ + I₂, Y = I₁ + I₂ if C = I₁ + I₂ (see Fig. 9(a) and Table 5). From Fig. 9(b) and Table 6, it can be seen that , when . The results given in Fig. 9(c) and Table 7 further show that X = I₁ ⊕ I₂ and Y = I₁ ⊕ I₂ when C = I₁ ⊕ I₂. Finally, X = I₁ ⊙ I₂ and Y = I₁ ⊙ I₂, owing to the case that C = I₁ ⊙ I₂ (see Fig. 9(d) and Table 8).

The above analyses show that different logic operations, such as logic AND, NAND, OR, NOR, XOR, and XNOR, can be implemented by the control of the logic operation between C and two logic inputs. In particular, under the same control logic signal and logic inputs, two logic outputs have the same logic operations between two logic inputs.

All of the above basic logic operations are implemented under static conditions. In the following, we further demonstrate the ability of some basic reconfigurable dynamic logic operations to implement the reconfiguration, such as AND, NAND, OR, NOR, XOR, and XNOR under different values of noise strength D as shown in Fig. 10. Here, μ = 2.0, K_x = 0 ns⁻¹, K_y = 10 ns⁻¹, T = 10 ns. From Figs. 10(a) and 10(b), it is found that when the values of D are 10⁷ and 10⁸, respectively, the different logic operations at different time periods can be implemented, controlling the logic operation between C and two logic inputs. For example, if C = I₁ · I₂ when the time t is between 100 ns and 200 ns, we obtain the logic AND operation, i.e., X = I₁ · I₂ and Y = I₁ · I₂; while t is between 200 ns and 300 ns, the logic NAND operation can be performed when , i.e., , ; with t varying from 300 ns to 400 ns, X = I₁ + I₂ and Y = I₁ + I₂ if C = I₁ + I₂, the logic outputs are logic OR operation; In the case that , the two logic outputs are of logic NOR operation, i.e., , , and when 400 ns ≤ t ≤ 500 ns; If C = I₁ ⊙ I₂, they are converted into the XNOR operation, i.e., X = I₁ ⊙ I₂, Y = I₁ ⊙ I₂ in the time period from 500 ns to 600 ns. Finally, with t being between 600 ns to 700 ns, the logic outputs are further converted into logic XOR operation due to the fact that C = I₁ ⊕ I₂. However, if D increases to 10⁹, according to the threshold mechanism given in Step 4, there exists one error bit in logic AND, NOR and XNOR operation in turn. Consequently, these three logic operations are invalid. For example, for logic AND operation during 150 ns and 170 ns, if (I₁, I₂) = (0, 1), σ_{x max} = 0.2671 and σ_{y max} = 0.2931. Since σ_{x max} > M and σ_{y max} > M, X = 1 and Y = 1, which indicates that one error bit occurs in the two logic outputs, respectively. Under this condition, it is impossible to achieve the logic AND operation. Similarly, logic operations NOR and XNOR cannot be implemented. With the value of D further increasing to 10¹⁰, for an arbitrary logic operation, σ_{x min} = 0.1471 and σ_{y min} = 0.1462. The two logic outputs are converted into 1 because σ_{x min} > M and σ_{y min} > M. This shows that all logic operations are invalid.

Fig. 9.

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	Fig. 9. (color online) Logic OR, NOR, XOR, and XNOR operations: (a) OR operation (b) NOR operation (c) XOR operation and (d) XNOR operation for μ = 2.0, Kx = 0 ns−1, Ky = 10 ns−1, and T = 10 ns where the black solid-line denotes the frequency detuning (control logic signal); blue line: the y-PC; bottle green line: the x-PC; red solid line: the three-level signals.

Table 5.

Table 5.

Table 5. Combinations of input and output for logic OR operation. . Einj(I1, I2) Control logicsignal C Threshold judgment OR gate: logic output X OR gate: logic output Y Einj I(0, 0) 0 σx max< M; σy max < M 0 0 Einj II(0, 1) 1 σx min > M; σy min > M 1 1 Einj II(1, 0) 1 σx min > M; σy min > M 1 1 Einj III(1, 1) 1 σx min > M; σy min > M 1 1

Table 5. Combinations of input and output for logic OR operation. .

Table 6.

Table 6.

Table 6. Combinations of input and output for logic NOR operation. . Einj(I1, I2) Control logic signal C Threshold judgment NOR gate: logic output X NOR gate: logic output Y Einj I(0, 0) 1 σx min > M; σy min > M 1 1 Einj II(0, 1) 0 σx max < M; σy max < M 0 0 Einj II(1, 0) 0 σx max < M; σy max < M 0 0 Einj III(1, 1) 0 σx max < M; σy max < M 0 0

Table 6. Combinations of input and output for logic NOR operation. .

Table 7.

Table 7.

Table 7. Combinations of input and output for logic XOR operation. . Einj(I1, I2) Control logic signal C Threshold judgment XOR gate: logic output X XOR gate: logic output Y Einj I(0, 0) 0 σx max < M; σy max < M 0 0 Einj II(0, 1) 1 σx min > M; σy min > M 1 1 Einj II(1, 0) 1 σx min > M; σy min > M 1 1 Einj III(1, 1) 0 σx max < M; σy max < M 0 0

Table 7. Combinations of input and output for logic XOR operation. .

Table 8.

Table 8.

Table 8. Combinations of input and output for logic XNOR operation. . Einj(I1, I2) Control logic signal C Threshold judgment XNOR gate: logic output X XNOR gate: logic output Y Einj I(0, 0) 1 σx min > M; σy min > M 1 1 Einj II(0, 1) 0 σx max < M; σy max < M 0 0 Einj II(1, 0) 0 σx max < M; σy max < M 0 0 Einj III(1, 1) 1 σx min > M; σy min > M 1 1

Table 8. Combinations of input and output for logic XNOR operation. .

Fig. 10.

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Fig. 10. (color online) For different values of noise strength D, the dynamic logic AND, NAND, OR, NOR, XOR, and XNOR operations, for μ = 2.0, Kx = 0 ns−1, Ky = 10 ns−1, T = 10 ns, and D = 107 (a), 108 (b), 109 (c), and 1010 (d). Black solid line represents the frequency detuning Δω (control logic signal) blue line the y polarization bottle green line the x polarization red solid line the three-level signals.

According to the chaotic system in an optically injected VCSEL, we propose a novel implementation scheme for reconfigurable dynamic AOCLOs by using the threshold mechanism and the PB evolution. Here, the frequency detuning between the tunable SG-DBR laser and the VCSEL is considered as a control logic signal. For different key parameters such as the injection current, the injected strength and the frequency detuning, we discuss the dynamic evolutions of the PB with the optically injected amplitude when the output of the VCSEL is in chaotic state. According to the evolutions, we find out an appropriate value of the control logic signal, and further explore the implementation methods of AOCLOs. The different AOCLOs, such as logic AND, NAND, OR, NOR, XOR, and XNOR, can be implemented, owing to the fact that the control logic signal meets different logic operations between two logic inputs. It is noted that with the same control of logic and logic inputs, two logic outputs have the same logic operation. In addition, the conversion among different logic operations can be realized under relatively low noise strength of the spontaneous emission, controlling the logic operation between the control logic signal and two logic inputs in different time periods. These results can be generally used in all-optical digital chaotic combinational logic operations, such as all-optical chaotic adder, decoder, etc. Also it is possible that the logic operation system with high speed, security and low power cost can be implemented based on the results presented in this paper.